1. Technical Field
This disclosure relates to integrated circuits and to guardbands that are implemented in connection with them.
2. Description of Related Art
Reduced processor reliability can be a negative repercussion of silicon scaling. Reliability concerns may stem from multiple factors, such as manufacturing imprecision that leads to several within-in die and die-to-die variations, ultra-thin gate-oxide layers that breakdown under high thermal stress, negative bias temperature instability (NBTI), and electromigration. Wearout may be one manifestation of these reliability concerns. Wearout may include the gradual timing degradation of devices and their eventual breakdown. Timing degradation may occur extremely slowly over time and can even be reversed in some instances, such as when degradation is caused by NBTI effects. When individual device variations are taken into consideration, this timing degradation may be hard to predict or accurately model.
Commercial products may make worst-case assumptions on timing degradation and may insert a guardband at design time to tackle wearout. Guardbanding may be achieved by reducing frequency or increasing voltage. However, guardbands may reduce performance of a chip during their entire lifetime just to ensure correct functionality during a small fraction of time near the end of this lifetime.
Another approach may be to use error detection and recovery methods. However, these can be costly.